Referring to FIG. 1, a block diagram of a chip 10 is shown illustrating a conventional design architecture. The chip 10 can include a number of input/output (I/O) cells 12, a number of hard macros 14 and core circuitry 16. The I/O cells 12 provide high performance interfaces for off chip signals. The hard macros 14 provide customized and/or optimized circuits for performing specific signal processing functions to support the high performance interface protocols.
According to conventional design rules, the hard macros 14 are placed right next to, or very near to, the I/O cells 12. Typically, the hard macros 14 are wired directly to the I/O cells 12 via metal routing 18 (i.e., a bus of wires running from the hard macro 14 to the I/O cells 12). The wires 18 can run at a very high speed. A conventional design practice is to specify a prohibited area (or dead region) 20 between the hard macros 14 and the I/O cells 12 to protect the wires 18 from noise that can be coupled from surrounding logic. No other routing or logic is allowed in the prohibited areas 20 in order to maintain the integrity of signals between the hard macros 14 and the I/O cells 12.
In conventional gate array designs, when a particular chip customization does not make use of the hard macros 14, the associated I/O cells 12 are unavailable. However, the I/O cells, 12 may support many more interfaces, such as proprietary interfaces, than the interface standard supported by the hard macros 14. Because the I/O cells 12 are a valuable resource, it would be desirable to have an architecture and/or method that allows the input/output cells 12 to be used even when the hard macros 14 are not.